In the structure of a trench Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) or vertical transistor, the gate of the transistor is formed in a trench on top of an epitaxial layer—and the source/drain regions are formed on both sides of the gate. This type of vertical transistor allows high current to pass through and channel to be turned on/off at a low voltage.
Referring to FIG. 1, a cross-sectional diagram of the structure of a trenched MOSFET is shown. In the prior art, the trenched MOSFET has a MOSFET structure comprises a N+-type silicon substrate (101), a N-type epitaxial layer (102), a plurality of trenches (121), an oxide film (122), a polysilicon (123), a plurality of gate oxide films (103), a plurality of trenched gates (104), a P-type base layer (105), a N+-type source layer (106), an interlayer oxide film (107), a plurality of source contact trenches (124), a P+-type base contact layer (108), a barrier metal layer (110), a plurality of contact metal plugs (111), a front metal layer (112), and a rear metal layer (113). The N+-type silicon substrate (101), the N-type epitaxial layer (102), the P-type base layer (105), and the N+-type source layer (106) are stacked in sequence; and each of the source contact trenches (124) has a P+-type base contact layer (108) at a bottom thereof. However, the P+-type region of prior art is located only at source contact trench bottom. The sidewall of source contact trench has no ohmic contact (due to low doping concentration of P base) with the contact metal plug resulting in poor ruggedness performance during UIS (Unclamp Inductance Switching) test. A parasitic N+/P/N is easily turned on when P base resistance from channel to the contact metal plug is high enough, causing device destroyed.
The present invention provides a new structure of trenched MOSFET structure with a trenched source contact which improves the lack of the prior art.